One of the last processes in the production of semiconductor integrated circuits (IC) is multi-leveled packaging, which includes expanding the electrode pitch of the IC chips containing the circuits for subsequent levels of packaging; protecting the chip from mechanical and environmental stress; providing proper thermal paths for channeling heat dissipated by the chip; and forming electronic interconnections. The manner in which the IC chips are packaged dictates the overall cost, performance, and reliability of the packaged chips, as well as of the system in which the package is applied.
Package types for IC chips can be broadly classified into two groups: hermetic-ceramic packages and plastic packages. A chip packaged in a hermetic package is isolated from the ambient environment by a vacuum-tight enclosure. The package is typically ceramic and is utilized in high-performance applications. A chip packaged in a plastic package, on the other hand, is not completely isolated from the ambient environment because the package is composed of an epoxy-based resin. Consequently, ambient air is able to penetrate the package and adversely affect the chip over time. Recent advances in plastic packaging, however, has expanded their application and performance capability. Plastic packages are cost-effective due to the fact that the production process is typically facilitated by automated batch-handling.
A recent development in the packaging of IC chips is the ball grid array (BGA) package, which may be utilized with either ceramic packages or plastic packages and involves different types of internal package structures. The BGA package uses multiple solder balls or bumps for electrical and mechanical interconnection of IC chips to other microelectronic devices. The solder bumps serve to both secure the IC chip to a circuit board and electrically interconnect the chip circuitry to a conductor pattern formed on the circuit board. The BGA technique is included under a broader connection technology known as “Controlled Collapse Chip Connection-C4” or “flip-chip” technology.
Flip chip technology can be used in conjunction with a variety of circuit board types, including ceramic substrates, printed wiring boards, flexible circuits, and silicon substrates. The solder bumps are typically located at the perimeter of the flip chip on electrically conductive bond pads that are electrically interconnected with the circuitry on the flip chip. Because of the numerous functions typically performed by the microcircuitry of a flip chip, a relatively large number of solder bumps are often required. The size of a flip chip is typically on the order of about thirteen millimeters per side, resulting in crowding of the solder bumps along the perimeter of the flip chip. Consequently, flip chip conductor patterns are typically composed of numerous individual conductors that are often spaced apart about 0.1 millimeter or less.
FIG. 1 illustrates a cross-section of a conventional BGA integrated circuit (IC) package structure 8 having a flip chip 10 which is inverted and bonded to a carrier substrate 20, such as a printed circuit board (PCB), for example. Fabrication of the flip chip 10 is begun by forming multiple bonding pads 16 on the surface of a chip substrate 12, in electrical contact with integrated circuits (not shown) fabricated on the chip substrate 12. A solder bump 18 is then bonded to each of the bonding pads 16. Each of the solder bumps 18 is typically spherical in configuration and extends through a passivation layer 14 formed on the surface of the chip substrate 12. A tin oxide layer 19 may coat the surface of each solder bump 18.
In assembly of the IC package structure 8, the flip chip 10 is subjected to a re-flow temperature of typically about 320° C. to re-flow the lead solder bumps 18 on the chip substrate 12. The flip chip 10 is then inverted and the solder bumps 18 are bonded with respective bond pads (not shown) on the carrier substrate 20. The re-flow heat partially melts the tin oxide layer 19 and bonds the underlying lead solder bumps 18 to the carrier substrate 20.
In an underfill process, an adhesive material 22, such as an epoxy, for example, is provided between the carrier substrate 20 and the chip substrate 12. As shown in FIG. 2A, the adhesive material 22 is initially dispensed in liquid form from a dispenser 24 onto the carrier substrate 20, at one corner of the flip chip 10. The adhesive material 22 is then drawn by capillary action between the carrier substrate 20 and the chip substrate 12, as shown in FIG. 2B. The hardened adhesive material 22, which typically has a high Young's modulus, attaches the flip chip 10 to the carrier substrate 20 and protects the solder bumps 18 from cracking in the finished IC package structure 8. A sealant material 23 is applied to the IC package structure 8, around the adhesive material 22. The hardened sealant material 23 has a low Young's modulus to prevent de-lamination of low dielectric constant intermetal dielectric (IMD) layers (not shown) on the chip substrate 12 during application.
During application of the adhesive material 22 to the IC package structure 8, stresses are applied to the brittle IMD layers (not shown) on the chip substrate 12. This frequently results in de-lamination of the IMD layer or layers, particularly at the corner of the flip chip 10 where the adhesive material 22 is applied. Accordingly, a novel underfill process is needed to prevent or reduce stresses applied to a flip chip, and particularly, to prevent de-lamination of low-k dielectric layers on a chip during application of an adhesive material to the structure.
An object of the present invention is to provide a novel underfill process for assembling a flip-chip integrated circuit package structure.
Another object of the present invention is to provide a novel underfill process which reduces stress on a flip chip during application of an adhesive material between the flip chip and a carrier substrate of the IC structure.
Still another object of the present invention is to provide a novel underfill process which reduces stress applied to a flip chip, which process includes providing a dam structure on a carrier substrate; attaching solder bumps of a flip chip to the carrier substrate; injecting an adhesive material between the flip chip and the carrier substrate at multiple injection points located along the edges of the flip chip; and injecting a sealant material around the adhesive material, wherein the dam structure reduces stress applied to the corners of the flip chip during the underfill process.